1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method for semiconductor fabrication supervision and optimization.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
The technologies underlying semiconductor processing tools have attracted increased attention over the last several years, resulting in substantial refinements. However, despite the advances made in this area, many of the processing tools that are currently commercially available suffer certain deficiencies. In particular, such tools often lack advanced process data monitoring capabilities, such as the ability to provide historical parametric data in a user-friendly format, as well as event logging, real-time graphical display of both current processing parameters and the processing parameters of the entire run, and remote, i.e., local site and worldwide, monitoring. These deficiencies can engender nonoptimal control of critical processing parameters, such as throughput accuracy, stability and repeatability, processing temperatures, mechanical tool parameters, and the like. This variability manifests itself as within-run disparities, run-to-run disparities and tool-to-tool disparities that can propagate into deviations in product quality and performance, whereas an ideal monitoring and diagnostics system for such tools would provide a means of monitoring this variability, as well as providing means for optimizing control of critical parameters.
Among the parameters it would be useful to monitor and control are process parameters related to metal deposition processing (MDP). Examples of such process parameters include the deposition thickness and deposition rate. The metal deposition processing (MDP) performance is typically affected by the consumption of the sputter target during consecutive processing runs. In particular, the deposition rate is affected by the sputter target life. Typically, the deposition rate decreases the longer the sputter target is used. Conventionally, this deposition rate decrease has been corrected manually by the process engineer, using a “seat of the pants” approach that may lead to misprocessing, e.g., the process may be continued for an incrementally longer duration. This may cause differences in wafer processing between successive runs or batches or lots of wafers, leading to decreased satisfactory wafer throughput, decreased reliability, decreased precision and decreased accuracy in the semiconductor manufacturing process.
However, traditional statistical process control (SPC) techniques are often inadequate to control precisely process parameters related to metal deposition processing (MDP) in semiconductor and microelectronic device manufacturing so as to optimize device performance and yield. Typically, statistical process control (SPC) techniques set a target value, and a spread about the target value, for the process parameters related to metal deposition processing (MDP). The statistical process control (SPC) techniques then attempt to minimize the deviation from the target value without automatically adjusting and adapting the respective target values to optimize the semiconductor device performance, and/or to optimize the semiconductor device yield and throughput. Furthermore, blindly minimizing non-adaptive processing spreads about target values may not increase processing yield and throughput.
Traditional control techniques are frequently ineffective in reducing off-target processing and in improving sort yields. For example, the wafer electrical test (WET) measurements are typically not performed on processed wafers until quite a long time after the wafers have been processed, sometimes not until weeks later. When one or more of the processing steps are producing resulting wafers that wafer electrical test (WET) measurements indicate are unacceptable, causing the resulting wafers to be scrapped, this misprocessing goes undetected and uncorrected for quite a while, often for weeks, leading to many scrapped wafers, much wasted material and decreased overall throughput.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.